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cy62157esl mobl ? 8-mbit (512k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-43141 rev. *c revised june 29, 2011 features very high speed: 45 ns wide voltage range: 2.2 v to 3.6 v and 4.5 v to 5.5 v ultra low standby power ? typical standby current: 2 ? a ? maximum standby current: 8 ? a ultra low active power ? typical active current: 1.8 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 44-pin thin small outline package (tsop) ii package functional description the cy62157esl is a high performance cmos static ram organized as 512k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. place the device into standby mode when deselected (ce high or both bhe and ble are high). the inpu t or output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), both the byte high enable and the byte low enable are disabled (bhe , ble high), or during an active write operation (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 18 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. 512k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 10 a 18 ce power down circuit bhe ble ce logic block diagram
cy62157esl mobl ? document #: 001-43141 rev. *c page 2 of 16 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 data retention characteristics ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 package diagram ....... .............. .............. .............. ........... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design support ....................... 16 products .................................................................... 16 psoc solutions ......................................................... 16
cy62157esl mobl ? document #: 001-43141 rev. *c page 3 of 16 pin configuration figure 1. 44-pin tsop ii (top view) product portfolio product range v cc range (v) [1] speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( ? a) f = 1mhz f = f max typ [2] max typ [2] max typ [2] max cy62157esl industrial 2.2 v?3.6 v and 4.5 v?5.5 v 45 1.8 3 18 25 2 8 notes 1. datasheet specifications are not guaranteed for v cc in the range of 3.6 v to 4.5 v. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 3 a 2 a 1 a 0 a 17 a 4 a 9 a 10 a 11 a 12 a 15 a 16 oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss 10 a 18 a 14 a 8 a 13
cy62157esl mobl ? document #: 001-43141 rev. *c page 4 of 16 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature................. ................?65 c to +150 c ambient temperature with power applied ............ ............... ................?55 c to +125 c supply voltage to ground potentia l ............. .. ?0.5 v to 6.0 v dc voltage applied to outputs in high-z state [3, 4] .........................................?0.5 v to 6.0 v dc input voltage [3, 4] ......................................?0.5 v to 6.0 v output current into outputs (low)............................. 20 ma static discharge voltage .......................................... >2001 v (mil-std-883, method 3015) latch up current...................................................... >200 ma operating range device range ambient temperature v cc [5] cy62157esl industrial ?40 c to +85 c 2.2 v?3.6 v, and 4.5 v?5.5 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [6] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?1.0 ma 2.4 ? ? v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma ? ? 0.4 4.5 < v cc < 5.5 i ol = 2.1 ma ? ? 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 4.5 < v cc < 5.5 2.2 ? v cc + 0.5 v il input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.6 v 2.7 < v cc < 3.6 ?0.3 ? 0.8 4.5 < v cc < 5.5 ?0.5 ? 0.8 i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma, cmos levels ?18 25ma f = 1 mhz ? 1.8 3 i sb1 [7] automatic ce power down current ? cmos inputs ce > v cc ?? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = v cc(max) ?2 8 ? a i sb2 [7] automatic ce power down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?2 8 ? a notes 3. v il (min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. 7. chip enable (ce ) needs to be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating.
cy62157esl mobl ? document #: 001-43141 rev. *c page 5 of 16 capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [8] description test conditions tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 ? c/w ? jc thermal resistance (junction to case) 13 ? c/w figure 2. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 th parameters 2.5 v 3.0 v 5.0 v unit r1 16667 1103 1800 ? r2 15385 1554 990 ? r th 8000 645 639 ? v th 1.20 1.75 1.77 v note 8. tested initially and after any design or proc ess changes that may affect these parameters .
cy62157esl mobl ? document #: 001-43141 rev. *c page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [9] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [10] data retention current ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v v cc = 1.5 v ? 2 5 ? a v cc = 2.0 v ? 2 8 t cdr [11] chip deselect to data retention time 0??ns t r [12] operation recovery time 45 ? ? ns figure 3. data retention waveform notes 9. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. 10. 10chip enable (ce ) needs to be tied to cmos levels to meet the i sb1 /i sb2 / i ccdr spec. other inputs can be left floating. 11. tested initially and after any design or process changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 13. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling chip enable signals or by disabling both bhe and ble . v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce or bhe .ble [13]
cy62157esl mobl ? document #: 001-43141 rev. *c page 7 of 16 switching characteristics over the operating range parameter [14] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low-z [15] 5 ? ns t hzoe oe high to high-z [15, 16] ? 18 ns t lzce ce low to low-z [15] 10 ? ns t hzce ce high to high-z [15, 16] ? 18 ns t pu ce low to power up 0 ? ns t pd ce high to power down ? 45 ns t dbe ble /bhe low to data valid ? 45 ns t lzbe ble /bhe low to low-z [15, 17] 5 ? ns t hzbe ble /bhe high to high-z [15, 16] ? 18 ns write cycle [18] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high-z [15, 16] ? 18 ns t lzwe we high to low-z [15] 10 ? ns notes 14. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less, timing ref erence levels of 1.5 v, input pulse levels of 0 to 3 v, and output loading of the specified iol/ioh as shown in the ac test loads and waveforms on page 5 . 15. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 16. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 17. if both byte enables are toggled together, this value is 10 ns. 18. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write.
cy62157esl mobl ? document #: 001-43141 rev. *c page 8 of 16 switching waveforms figure 4. read cycle no.1: address transition controlled . [19, 20] figure 5. read cycle no. 2: oe controlled [20, 21] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 19. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 20. we is high for read cycle. 21. address valid before or similar to ce , bhe , ble transition low.
cy62157esl mobl ? document #: 001-43141 rev. *c page 9 of 16 figure 6. write cycle no 1: we controlled [22, 23, 24] figure 7. write cycle 2: ce controlled [22, 23, 24] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 25 t bw t sce data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe /ble note 25 notes 22. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. 23. data i/o is high impedance if oe = v ih . 24. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 25. during this period, the i/os are in output state. do not apply input signals.
cy62157esl mobl ? document #: 001-43141 rev. *c page 10 of 16 figure 8. write cycle 3: we controlled, oe low [26, 27, 28] figure 9. write cycle 4: bhe /ble controlled, oe low [26, 27, 28] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 29 ce address we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 29 data i/o address ce we bhe /ble notes 26. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set up and hold timing must be referenced to the edge of the sig nal that terminates the write. 27. data i/o is high impedance if oe = v ih . 28. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 29. during this period, the i/os are in output state. do not apply input signals.
cy62157esl mobl ? document #: 001-43141 rev. *c page 11 of 16 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high-z deselect/power down standby (i sb ) x [30] x x h h high-z deselect/power down standby (i sb ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) lhlhldata out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high-z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high-z read active (i cc ) l h h l l high-z output disabled active (i cc ) l h h h l high-z output disabled active (i cc ) l h h l h high-z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high-z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high-z write active (i cc ) note 30. the ?x? (don?t care) state for the chip enable in the truth table refers to the logic state (either high or low). intermedia te voltage levels on this pin is not permitted.
cy62157esl mobl ? document #: 001-43141 rev. *c page 12 of 16 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62157ESL-45ZSXI 51-85087 44-pin thin small outline package type ii (pb-free) industrial ordering code definitions temperature range zsx = 44-pin tsop ii (pb-free) 45 = speed grade separator sl = voltage range (3 v typical; 5 v typical) e = process technology 90 nm buswidth = 16 density = 8-mbit family code: mobl sram family company id: cy = cypress cy 45 xxx 621 5 7 e sl - i
cy62157esl mobl ? document #: 001-43141 rev. *c page 13 of 16 package diagram figure 10. 44-pin tsop ii, 51-85087 max min. dimension in mm (inch) (optional) can be located anywhere in the bottom pkg ejector mark z a z z z z x a 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) top view bottom view plane seating 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) base plane 0.10 (.004) 11.938 (0.470) pin 1 i.d. 44 1 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 22 23 51-85087-*c
cy62157esl mobl ? document #: 001-43141 rev. *c page 14 of 16 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degrees celsius ? a microamperes ma milliamperes mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts
cy62157esl mobl ? document #: 001-43141 rev. *c page 15 of 16 document history page document title: cy62157esl mobl ? 8-mbit (512k x 16) static ram document number: 001-43141 rev. ecn no. issue date orig. of change description of change ** 1875228 see ecn vkn/ aesa new data sheet *a 2943752 06/03/2010 vkn added contents added footnote for t he isb2 parameter in electrical characteristics added footnote related to chip enable in truth table updated package diagram added sales, solutions, and legal information *b 3109266 12/13/2010 pras changed ta ble footnotes to footnotes. added ordering code definitions. *c 3295175 06/29/2011 rame remove referenc e to an1064 sram system guidelines. added i sb1 and i ccdr to footnotes 7 and 10. added footnote 8 for capacitance and thermal resistance section. updated ordering code definitions . added document conventions . updated table of contents.
document #: 001-43141 rev. *c revised june 29, 2011 page 16 of 16 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders. cy62157esl mobl ? sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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